1. Field of Invention
This invention relates to vertical or horizontal type junction field effect transistors and methods for manufacturing same and more particularly to field effect transistors wherein the channel-gate structure is formed by a diffusion technique.
2. Prior Art
In general, junction field effect transistors (hereinafter referred to as FET) are broadly classified into horizontal and vertical types. Conventionally, the horizontal type junction FET is fabricated by a method in which on the surface of a semi-conductor substrate of a first conductivity type a semi-conductor layer of a second conductivity type which is opposite to the first conductivity type is formed by epitaxial growth or a diffusion technique. By such a method in the surface of the semi-conductor substrate layer of the first conductivity type a gate region is formed by diffusion so as to combine a channel region of a second conductivity type between the first conductivity type gate region and the first conductivity portion of the substrate. On the other hand, a vertical type junction FET is fabricated by forming on the surface of a semi-conductor substrate of a first conductivity type which is the drain region a gate region of a second conductivity type opposite to the first conductivity type by diffusion in a predetermined shape such as a mesh and stripe and growing a source region of a first conductivity type by epitaxial method covering the gate region so that the gate region is buried in the structure.
In the conventional FET's since the area of the gate P-N junction is comparatively large, the gate-source capacitance is large so that the high frequency characteristics of the FET are impaired. Furthermore, since the width and length of the channel are determined substantially by a gate diffusion pattern, it is difficult to attain a minute channel structure of a high purity concentration having a high gain and it is also difficult to effectively utilize the chip area with such a minute structure.
In addition, the above described conventional method of manufacturing horizontal type or vertical type junction FET has the additional problems described below. To enhance the power utilization efficiency, it is desirable to make the saturation voltage or on resistance low. However, when the impurity concentration of the channel is increased in order to lower this voltage or resistance, a depletion layer becomes difficult to spread. On the other hand, the pinch-off voltage or cut-off voltage increases and the drain break-down voltage lowers. These contradictory results in the characteristics are attributed to the fact that in the prior art method the channel region is prepared in the same manufacturing step with the source or drain region so that the channel region has the same impurity concentration as the source or drain. It has therefore been considered as a solution to form the channel region and the source or drain region in separate steps. By merely providing such individual steps, however, the number of steps increases and the yield of the product decreases, which is undesirable from the view point of cost production.